View ISL6296ADRTZ-T_4132374.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL6296A
Data Sheet October 31, 2007 FN6567.0
FlexiHashTM For Battery Authentication
The ISL6296A is a highly cost-effective fixed-secret hash engine based on Intersil's FlexiHashTM technology. The device's authentication is achieved through a challenge response scheme, which is customized for low-cost applications where cloning via eavesdropping without knowledge of the device's secret code is not economically viable. When used for its intended applications, the ISL6296A offers the same level of effectiveness as other significantly more expensive high maintenance monetarygrade hash algorithm and authentication schemes. The ISL6296A has a wide operating voltage range and is suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a 3-cell series NiMH battery pack. The ISL6296A can also be powered by the XSD bus when the bus pull-up voltage is 3.3V or higher. The device connects directly to the cell terminals of a battery pack and includes on-chip voltage regulation circuit, POR and a non-crystal based oscillator for bus timing reference. Communication with the host is achieved through a single-wire XSD interface (a light-weight subset of Intersil's ISD bus interface). The XSD bus is compatible for use with serial ports offered by all 8250 compatible UART's or a single GPIO (General Purpose Input and Output) pin of a microprocessor. A clone prevention solution utilizing the ISL6296A offers safety and revenue protection at the lowest cost and power and is suitable for protection against after-market replacement for a wide variety of low-cost applications.
Features
* Challenge-response based authentication scheme using 32-Bit challenge code and 8-Bit authentication code. * Fast and flexible authentication process. Multi-pass authentication can be used to achieve the highest security level if necessary. * 16x8 OTP ROM stores up to three sets of 32-Bit host selectable secrets with additional programmable memory for storage of up to 48-bits of ID code and/or pack information. * FlexiHash engine uses two sets of 32-Bit secrets for authentication code generation. * Non-unique mapping of the secret key to an 8-Bit authentication code maximizes hacking difficulty due to need for exhaustive key search (superior to SHA-1). * Supports 1-cell Li-Ion/Li-Poly and 3-cell series NiMH battery packs (2.6V ~ 4.8V operation), or powered by the XSD bus. * XSD single-wire host bus interface communicates with all 8250-compatible UART's or a single GPIO. Supports CRC on read data and transfer bit-rate up to 23kbps. * True "Zero Power" Sleep mode - automatically entered after a bus inactivity time-out period * 5 Ld SOT-23 and 8 Ld TDFN (2mmx3mm) packages * -20C to +85C operating temperature range * Pb-free (RoHS compliant)
Pinouts
ISL6296A (5 LD SOT-23) TOP VIEW
VSS 1 NC 2 VDD 3 4 TIO 5 XSD
Applications
* Battery Pack Authentication * Printer Cartridges * Add-on Accessories * Other Non-Monetary Authentication Applications
Related Literature
* Application Note AN1165 "ISL6296 Evaluation Kit" * Application Note AN1167 "Implementing XSD Host Using a GPIO" * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
ISL6296A (8 LD 2X3 TDFN) TOP VIEW
VSS NC NC VDD 1 2 3 4 8 7 6 5 XSD NC NC TIO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved. FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6296A Ordering Information
PART NUMBER (Note) ISL6296ADHZ-T* ISL6296ADRTZ-T* ISL6296EVAL1 PART MARKING 296A 96A ISL6296 Evaluation Kit TEMP. RANGE (C) -20 to +85 -20 to +85 PACKAGE (Pb-free) 5 Ld SOT-23 Tape and Reel 8 Ld 2x3 TDFN Tape and Reel PKG. DWG. # P5.064 L8.2X3A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6567.0 October 31, 2007
ISL6296A
Absolute Maximum Ratings (Reference to GND)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to VDD+0.5V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) SOT-23 Package (Note 1) . . . . . . . . . . 200 N/A 2x3 TDFN Package (Notes 2, 3) . . . . . 70 10.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +125C Maximum Storage Temperature Range . . . . . . . . . .-40C to +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-20C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER DC CHARACTERISTICS Supply Voltage
Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: TA = -20C to +85C; VDD = 2.6V to 4.8V. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VDD
During normal operation During OTP ROM programming
2.6 2.8 2.3 11 1.9 1.5
38 40 0.15 250 2.5 12 2.2 1.8
4.8 4.8 55 65 0.5 500 2.7 13 2.4 2.1
V V A A A A V V V V
Run Mode Supply Current (Exclude I/O Current) Sleep Mode Supply Current OTP Programming Mode Supply Current Internal Regulated Supply Voltage Internal OTP ROM Programming Voltage POR Release Threshold POR Assertion Threshold XSD PIN CHARACTERISTICS XSD Input Low Voltage XSD Input High Voltage XSD Input Hysteresis XSD Internal Pull-Down Current
IDD
VDD = 4.2V VDD = 4.8V
IDDS IDDP VRG VPP VPOR+ VPOR-
VDD = 4.2V, XSD pin floating For ~ 1.8ms duration per write operation Observable only in test mode Observable only in test mode
VIL VIH VHYS IPD VDD = 2.6V VDD = 4.2V VDD = 4.8V
-0.4 1.5 -
400 0.8 1.2 1.8 6
0.5 VDD+ 0.4V 2.0 2.5 0.4 2 50 -
V V mV A A A V s ns pF
XSD Output Low Voltage XSD Input Transition Time XSD Output Fall Time XSD Pin Capacitance
VOL tX tF CPIN
IOL = 1mA 10% to 90% transition time 90% to 10%, CLOAD = 12pF
3
FN6567.0 October 31, 2007
ISL6296A
Electrical Specifications
PARAMETER Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: TA = -20C to +85C; VDD = 2.6V to 4.8V. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables) Programming Bit Rate XSD Input Deglitch Time Device Wake-Up Time Device Sleep Wait Time Auto-Sleep Time-Out Period OTP ROM Write Time Hash Calculation Time Soft-Reset Time tWDG tWKE tSLP tASLP tEEW tHASH tSRST x = 0.5 to 4 Pulse width narrower than the deglitch time will not cause the device to wake up From falling-edge of break command issued by host to falling-edge of break command returned by device From when the `11' Opcode is detected to the shut-off of the internal regulator From the last transition detected on the XSD bus to the device going into sleep mode From the last BT of the 2nd write data frame to when device is ready to accept the next instruction From the last BT of the Challenge Code Word from the host to the Authentication Code being available for read From the last BT of the Soft-Reset instruction issued by the host to the falling-edge of break command returned by device 2.89 7 130 4 160 0.6 1.8 1 23.12 20 210 1.9 30 kHz s s s s ms BT s
Pin Descriptions
ISL6296ADHZ-T ISL6296ADRTZ-T (5 LD SOT-23) (8 LD TDFN) 1 2 3 4 5 1 2, 3, 6, 7 4 5 8 PIN NAME VSS NC VDD TIO XSD System ground. No connection. Supply voltage. Production test I/O pin. Used only during production testing. Must be left floating during normal operation. Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input and an open-drain output. An appropriate pull-up resistor is required on the host side. DESCRIPTION
4
FN6567.0 October 31, 2007
ISL6296A Typical Applications
PACK+ R1 100 XSD D1 5.1V PACKR2 100 PROTECTION C1 0.1F
XSD
ISL6296A VSS
VDD
FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296A POWERED BY THE BATTERY
PACK+ R1 100 XSD D1 5.1V PACK-
XSD
ISL6296A VSS
VDD C1 0.1F
PROTECTION
FIGURE 2. TYPICAL APPLICATION WITH THE ISL6296A POWERED BY THE XSD BUS
Block Diagram
VDD
ESD DIODE
POR/2.5V REGULATOR
OSCILLATOR ANALOG DIGITAL
XSD
XSD COMM INTERFACE
DCFG (1 BYTE) DTRM (1 BYTE) SECRET #1 (4 BYTES) SECRET #2 (4 BYTES) SECRET #3 (4 BYTES) GENERAL PURPOSE (2 BYTES) 16 BYTES OTPROM CONTROL/STATUS/ TEST INTERFACE
AUTH SESL CHLG FLEXIHASH+ TM ENGINE
ESD DIODE
MSCR
STAT
TIO
VSS
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
5
FN6567.0 October 31, 2007
ISL6296A Theory of Operation
The ISL6296A contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage of up to 96-bits of secret for the authentication and other user information. A 32-bit CRC-based hash engine (FlexiHashTM) calculates the authentication result immediately after receiving a 32-bit random challenge code. The communication between the ISL6296A and the host is implemented through the XSD single-wire communication bus. Major functions within the ISL6296A include the following, as shown in Figure 3: * Power-on reset (POR) and a 2.5V regulator to power all internal logic circuits. * 16x8-Bit (16-Byte) OTP ROM as shown in Table 8. The first part (two bytes) contains the device default configuration (DCFG) information (such as the device address and the XSD communication speed) and the default trimming (DTRM) information (such as the internal oscillator frequency trimming). The second part contains two groups (12-Byte) of memory that can be independently locked out for the storage of up to three sets of secret. The last part provides two additional bytes of space for general-purpose information. * Control functions, including master control (MSCR) and status (STAT) registers (as shown in Table 9), interrupt generation, and the test-related interface. * FlexiHashTM engine that includes the 32-Bit CRC-based hash engine, secret selection register, challenge code register and the authentication result register. Table 10 shows all the registers. * XSD communication bus Interface. The XSD device address and the communication speed are configured in the DCFG address in the OTPROM, as given in Table 8. * Time Base Reference. The following explains in detail the operation of the ISL6296A.
HOST BREAK DEVICE BREAK XSD BUS WAVEFORM
ISL6296A is ready and waiting for a bus transaction from the host.
HOST BREAK DEVICE BREAK XSD BUS WAVEFORM 60s TYP 1.391 BT D
FIGURE 4A. WHEN THE HOST POWER-ON BREAK IS WIDER THAN 60s
FIGURE 4B. WHEN THE HOST POWER-ON BREAK IS NARROWER THAN 60s FIGURE 4. POWER-ON BREAK SIGNAL TO WAKE-UP THE ISL6296A FROM SLEEP MODE
Power-On Reset (POR)
The ISL6296A powers up in Sleep mode. It remains in Sleep mode until a power-on `break' command is received from the host through the XSD bus. The initial power-on `break' can be of any pulse width, as long as it is wider than the XSD input deglitch time (20s). Once the `break' command is received, the internal regulator is powered up. About 20s after the falling edge of the power-on `break', an internal POR circuit releases the reset to the digital block, and a POR sequence is started. During the POR sequence, the ISL6296A initializes itself by loading the default device configuration information from pre-assigned locations within the OTP ROM memory. After initialization, a `break' command is returned to the host to indicate that the
Note that the ISL6296A will initiate the power-on sequence without waiting for the power-on `break' signal to return to the high state. If the host sends an initial `break' pulse wider than 60s, the device-ready `break' returned by the ISL6296A will likely be merged with the pulse sent by the host and, therefore, may not be detectable. Figure 4 illustrates the waveforms during the Power-on Reset. Figure 4A represents the case when the power-on `break' rising edge occurs after the device starts sending the `break'. Figure 4B represents the case when the power-on `break' finishes before the device sends its `break'. The device break signal is always 1.391 times of the device bit-time (BT, see "XSD Host Bus Interface" on page 10 for more details). Either case in Figure 4 will wake-up the device successfully if the device is in the sleep mode. Note that It is important to keep in mind that a narrow `break' signal will be taken as a normal bit signal and cause errors if the device is not in the sleep mode. For this reason, the narrow power-on `break' signal should be used only if the user has to see the returned `break' signal.
Auto-Sleep
While the ISL6296A is powered up and there is no bus activity for more than about 1 second, the device will automatically return to Sleep mode. Sleep mode can be entered independent of whether the XSD bus is held high or low. While the ISL6296A is in Sleep mode, it is recommended that the XSD bus be held low to eliminate current drain through the XSD-pin internal pull-down current.
FN6567.0 October 31, 2007
6
ISL6296A
Auto-Sleep mode can be disabled by clearing the ASLP bit in the MSCR register. By default, Auto-Sleep is always enabled at power-up and after a soft reset. Auto-sleep function can be permanently disabled by clearing the 0-00[2] bit (the ASLP bit in DCFG) during OTP ROM programming. of operation based on information stored within DCFG address of the OTP ROM. The default configuration is loaded into the master control (MSCR) and the status (STAT) registers. Functions that are configured by OTP ROM settings include: e. Device address (DAB[1:0]) f. XSD bus speed (SPD[1:0]) g. Register default settings (eINT and ASLP) h. ROM read/write lock-out (SLO[1:0]) The ISL6296A incorporates interrupt functions to allow the host to be quickly informed of device status and error conditions. Available interrupts are summarized in Table 1. When an interrupt enable bit is set, a `break' command is sent to the host whenever its corresponding interrupt status bit is set. After this, the host should read the STAT register immediately. If the following instruction frame from the host does not access the STAT register, another `break' will be sent immediately after receiving the full instruction frame. This process is repeated until the host reads from the STAT register. Upon reading of the STAT register, all status bits will be cleared. Refer to the MSCR and STAT register descriptions for a detailed explanation of the interrupt functions.
OTP ROM
The 16-Byte OTP ROM memory is based on EEPROM technology and is incorporated into the ISL6296A for storage of non-volatile information. OTP ROM contents (refer to Table 8) can include, but not limited to: 1. Device default settings (address 0-00) 2. Factory programmed trim parameters (address 0-01) 3. Device authentication secrets (address 0-02 to 0-0D) 4. Pack information and ID (address 0-0E and 0-0F) The memory can be written multiple times before two lock-out bits (SLO[1:0] in DCFG, see Table 8) being set. The SLO[1] (bit 1) locks out the memory between 0-02 and 0-09 and the SLO[0] (bit 0) locks out the memory between 0-0A to 0-0D. These two bits can be set independently. Prior to lock-out, the memory can be written and read directly through the XSD bus interface. After lock-out, writing to all ROM addresses and reading from secret code locations will be permanently disabled after performing a reset cycle. Writing to the EEPROM requires the supply voltage at the VDD pin be maintained at a minimum of 2.8V. Failure to do so may result in unreliable ROM programming or total write failure. The OTP ROM must be written two bytes at a time, but 2, 4 or 16-bytes of data can be read by the host in a single bus transaction. Only even addresses are allowed in OTP ROM read/write. A 16-Byte read with CRC allows the entire ROM content to be quickly verified by simply checking the CRC byte. The DTRM address stores the default trimming parameters and is a read-only address. The DCFG and DTRM (0-00 and 0-01 addresses) need to be written simultaneously but the data to the DRTM address is ignored. The OTP ROM writing process takes approximately 1.8ms per two-Byte. While the write process is taking place, no bus transaction is allowed. Attempting to access the ISL6296A during an on-going write process will result in the device ignoring the access instruction and issuing an interrupt to the host. The OTP ROM programming is register-based and may be performed at the pack manufacturer's facility.
FlexiHashTM Engine
The FlexiHashTM engine contains a 32-Bit CRC-based hash engine and three registers. Table 10 lists the three registers. The 1-byte secret selection (SESL) register selects two sets of secret (32-bit each) from the OTP ROM to program the hash engine. The 4-byte challenge code register (CHLG) receives the challenge code from the host through the XSD bus. Once the challenge code is received, the hash engine generates a 1-Byte authentication result code and stores in the AUTH register for the host to read. Figure 5 shows the data flow of the authentication process. The following sections describe the authentication process and FlexiHashTM encoding scheme in detail. THE DEVICE AUTHENTICATION PROCESS To start an authentication process, the host sends a `break' command to wake up the ISL6296A. Then the host writes to the SESL register to select the two sets of secrets to be used for authentication code generation. After that, the host generates a pseudo-random 4-Byte challenge code to input into the CHLG register to initiate the authentication process. Upon receiving the fourth byte of the challenge code, the ISL6296A immediately starts computing the authentication code. Once the computation is complete, the 8-bit authentication code is made available at the AUTH register for the host to read out. The host reads this code and, concurrently, calculates the correct authentication code based on the challenge code it generated and the same secrets chosen, and finally compares the result with the authentication code read from the device. If the codes do not
Device Control and Status
The ISL6296A has a control and a status register. The control register can be read and written by the host but the status register is read only. Both registers contain the device configuration information (see Table 9). The status register also contains the device status information that may lead to an interrupt signal to the host. Following a host-initiated power-on `break' signal or soft reset command, the ISL6296A will configure its default mode
7
FN6567.0 October 31, 2007
ISL6296A
match up, the device is a fake device and the host may shut itself down. The flow chart in Figure 6 summarizes the process that the host needs to execute.
32-BIT PSEUDO-RANDOM CHALLENGE WORD FROM HOST 64-BIT SECRET 32-BIT HASH FUNCTION 32-BIT HASH SEED START
WAKE UP ISL6296A USING A REGULAR BREAK SIGNAL
SELECT HASH FUNCTION AND SEED BY WRITING TO SESL REGISTER FLEXIHASH ENGINE
SEND A 32-BIT RANDOM CHALLENGE TO CHLG REGISTER READ THE AUTHENTICATION RESULT FROM AUTH REGISTER, AFTER WAITING FOR 1 BTD CALCULATE THE EXPECTED AUTHENTICATION RESULT BASED ON THE SAME SECRETS
8-BIT AUTHENTICATION CODE
FIGURE 5. AUTHENTICATION PROCESS FLOW DIAGRAM
It is recommended that device authentication be done once in a while to maximize its effectiveness. Before a new challenge code can be accepted by the device, the SESL register must be re-written again to ensure that the original seeds are re-loaded from the OTP ROM into the hash engine prior to performing the next authentication code calculation. Failure to follow the sequence will result is a bus error, causing the sBER flag to be set in the STAT register. SET-UP FOR DEVICE AUTHENTICATION SUPPORT To configure the host and the ISL6296A to support device authentication function, the pack manufacturer will need to select at least 2 sets of 32-bit secret codes. For greater security, a third set of 32-bit secret may be used. The FlexiHashTM engine requires two sets of 32-bit secrets for use in its hash calculation; the first set to define its hash function, and the second set to initialize its seed for hash calculation. These two sets can be selected from the same secret location. The chosen secret codes are to be kept by the pack manufacturer and maintained at utmost confidentiality. After the secrets have been determined, they are written into the device's OTP ROM. After verification that the codes have been written in correctly, the relevant secrets lock-out bits at ROM address location 0-00 should be set. Once set, the lock-out bits can no longer be cleared. Thereafter, read/write access to the secret information will no longer be possible, and the secret codes are made available only to the FlexiHashTM engine for generation of authentication code based on a challenge code input from the host. On the host side, the same secret codes will need to be kept, and the same FlexiHashTM engine will have to be implemented in firmware. Refer to the Application Note AN1166 for detailed information of firmware implementation. It is important that the secret codes be stored scrambled in the host's non-volatile memory so that the secret information cannot be easily revealed by monitoring signal transfer on the host PCB.
THE TWO RESULTS MATCH?
NO
YES
SHUT DOWN THE SYSTEM
END
FIGURE 6. FLOW CHART FOR AUTHENTICATION PROCESS
THE HASH ENGINE The hash engine consists of 4 separate programmable 8-bit CRC calculators. Two sets of 32-bit secret codes are use by the hash engine for authentication code generation. The first set is used to define the CRC polynomial as well as the input selection for each of the CRC calculators. The second is used as initial seeds for the CRC calculations. Outputs of the 4 CRC calculators are logically combined to produce the 8-Bit output of the overall FlexiHashTM engine. The Block Diagram of the FlexiHash engine is illustrated in Figure 7. More detailed description on the hash engine can be found in Application Note AN1166.
8
FN6567.0 October 31, 2007
ISL6296A
NA[7:0] 8 XI MUX BN CN DN 8-BIT CRC CALCULATOR 8 XA[7:0] MA[7:6] POLYNOM = 1 + XMA[2:0] - XMA[5:3] + X8 NB[7:0] 8 AN MUX XI CN DN 8-BIT CRC CALCULATOR 8 XB[7:0] MB[7:6] POLYNOM = 1 + XMB[2:0] - XMB[5:3] + X8 NC[7:0] 8 AN MUX BN XI DN 8-BIT CRC CALCULATOR 8 XC[7:0] MC[7:6] POLYNOM = 1 + XMC[2:0] - XMC[5:3] + X8 ND[7:0] 8 AN MUX BN CN XI 8-BIT CRC CALCULATOR 8 XD[7:0] MD[7:6] POLYNOM = 1 + XMD[2:0] - XMD[5:3] + X8 DAN CN BN AN
Y[7:0] = XA[7:0] S2R{XB[7:0]} S4R{XC[7:0]} S6R{XD[7:0]}
LEGEND: XI AN,BN,CN,DN XA,XB,XC,XD MA,MB,MC,MD NA,NB,NC,ND SNR{ } Y[7:0] 32-BIT CHALLENGE CODE WORD SERIAL BIT-STREAM CRC CALCULATOR SERIAL OUTPUTS CRC CALCULATOR 8-BIT PARALLEL OUTPUTS CRC POLYNOMIAL AND INPUT SELECTION CODES CRC REGISTER INITIALIZATION SEEDS N-BIT CYCLICAL RIGHT SHIFT FUNCTION 8-BIT AUTHENTICATION CODE OUTPUT
FIGURE 7. BLOCK DIAGRAM OF THE FLEXIHASH ENGINE
9
FN6567.0 October 31, 2007
ISL6296A
XSD Host Bus Interface
Communication with the host is achieved through XSD, a light-weight subset of Intersil's ISD single-wire bus interface. XSD is a programmable-rate, pseudo-synchronous, bidirectional, host-initiated, instruction-based, serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication. The communication protocol is optimized for efficient transfer of data between the device and the host. The following list outlines the features supported by the XSD bus interface: * Programmable bit rate up to 23kbps * Up to 2 devices can be connected to the host and addressed separately * 16-Bit host instruction frame supports multi-Byte register read and write * Built-in communication error detection * CRC generation capability * Supports interrupt signaling * Integrated bus inactivity detector for automatic activation of sleep mode XSD BUS PHYSICAL MODEL The physical model of the XSD bus is shown in Figure 8. The model shows a single-wire connection between the host and the device, not including the ground signal. The input logic on the device side is designed to be compatible with any voltage between 1.8V to 5.0V. The host interface should contain an open-drain or open-collector output. The pull-up resister RPU can be connected either to the host supply voltage VDDH or the device supply voltage VDDD. Typically, the host supply voltage should be used for pull-up. DATA TRANSFER PROTOCOL To initiate a transaction, the host first sends a 16-bit instruction frame to the device, followed by data byte frame(s) if the instruction is a write operation. The instruction frame consists of a chip-select code, operation code, register bank and address pointer and number of data bytes information, as shown in Figure 10. If the instruction is a read operation, the device will return 1 to 17 byte frames of data back to the host. The serial data transfer always takes place with the LSB first. The following explains the bus symbols. The transaction frames are introduced in later sections. BUS SIGNALING SYMBOLS The XSD bus is nominally held high. Various bus symbols and commands are generated by active-low pulse width modulation. Following are the set of valid bus signaling symbols supported by the XSD interface: 1) Break (Issued by Host): * Used to wake the device up from Sleep mode (Note: a narrow `break' can also be used to wake up the device from the Sleep mode, as described in "Power-On Reset (POR)" on page 6) * Used to reset the device's XSD bit counters and time qualifiers * Used to signal a change in communication channel (from one slave device to another) 2) Break (Issued by Device): * Used as `device-ready' indication to the host (after a Soft-reset or wake-up from Sleep mode) * Used as an interrupt indicator 3) `1' Symbol: * Used for instruction and data coding 4) `0' Symbol: * Used for instruction and data coding SYMBOL TIMING DEFINITIONS Symbol timings are defined in terms of bit-time (BT), determined by the selected bus transfer bit-rate pre-programmed into the device's OTP ROM location 000[5:4]. Selectable bus speeds are: 2.89kHz (x = 0.5), 5.78kHz (x = 1), 11.56kHz (x = 2) and 23.12kHz (x = 4). An instruction or data frame consists of a sequence of `1' and/or `0' symbols. Figure 9 illustrates the timing definitions. A `1' symbol is nominally 0.3 BT wide while a `0' symbol is nominally 0.7 BT wide. One `1' or `0' symbol is represented in each BT period. Any detected pulse width less than 0.124 BT wide will be interpreted as a glitch and will result in a bus error. Tables 2 and 3 summarize the timing definitions of all the supported symbols and bus signaling.
TABLE 1. INTERRUPT EVENT SUMMARY CONDITION OTP ROM Write-in-Progress XSD Bus Error Register Access Error INTERRUPT ENABLE BIT eEEW (fixed) eINT eINT INTERRUPT STATUS FLAG sEEW sBER sACC INTERRUPT EVENT Accessing the ISL6296A during an on-going ROM write process (used only during initial OTP ROM programming). XSD bus error or invalid instruction frame detected. Improper authentication sequence detected. Accessing protected registers.
10
FN6567.0 October 31, 2007
ISL6296A
VDDH VDDD DEVICE HOST
TX
OPEN-DRAIN Open-Drain PORT-PIN Port Pin
RPU
ESD Diode DIODE
RX
RX
ESD ESD DIODE Diode
1.5A
6pF
TX
FIGURE 8. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS
tb t0 tg XSD t1
glitch GLITCH
1
BT
0
BREAK Break
FIGURE 9. THE BUS SIGNAL TIMING DIAGRAM
TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER Bit Time Deglitch period `1' pulse width `0' pulse width `break' time SYM BTH tg t1H t0H tbH x = 0.5, 1, 2, or 4 PW (Pulse Width) less than this will result in a frame error PW in this range will be interpreted as a `1' code PW in this range will be interpreted as a `0' code PW in this range will be interpreted as a `break' command 0.227 0.591 1 DESCRIPTION MIN TYP 173.6/x 0.124 0.453 0.824 100 MAX UNIT s BTH BTH BTH BTH
NOTE: Unless otherwise stated, all pulse width (PW) referenced are with respect to an active-low pulse. TABLE 3. DEVICE TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER Bit Time `1' pulse width `0' pulse width `break' time SYM BTD t1D t0D tbD x = 0.5, 1, 2, or 4 `1' code transmit pulse width `0' code transmit pulse width PW in this range will be interpreted as a `break' command DESCRIPTION MIN 164.2/x TYP 172.8/x 0.304 0.696 1.391 MAX 181.4/x UNIT s BTD BTD BTD
11
FN6567.0 October 31, 2007
ISL6296A
15 BYTES ADDRESS BANK 0 OPCODE CS
FIGURE 10. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION TABLE 4. DEFINITION OF THE OPCODE FIELD OPCODE 00 01 10 11 DESCRIPTION Write Operation Read Operation (normal) Write to device register Read from device register ACTION
Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame. Sleep Mode Activation Immediately sets the device in Sleep mode. Note: After detecting the `11' Opcode, the device immediately enters sleep mode. If more than 3 bits sent, subsequent pulses may wake the device up again. TABLE 5. BANK FIELD DEFINITION. BANK 00 01 10 11 MEMORY/REGISTER BANK SELECTION OTP ROM Control and Status Registers Device Authentication Registers Test Registers (Reserved)
Access Instruction Frame
The XSD access instruction frame is shown in Figure 10. The instruction frame consists of 16-bits of digital signal with the contents described as following. CS FIELD The CS field is a 1-Bit Chip Address Selection. An initial 1-Bit Chip Address code of `0' is pre-programmed into the device's OTP ROM address location 0-00[7:6] at the time of chip manufacture and may be re-programmed by the pack manufacturer if needed. If the CS code in the instruction does not match the device's Chip Address code, the instruction, and any subsequent frames that follow, will be ignored until a break command is received. OPCODE FIELD The OPCODE is a 2-Bit field defines the operation of the transaction following the instruction frame. The operations are described in Table 4. BANK FIELD The memories in the ISL6296A are divided into four banks. The BANK field is defined in Table 5.
ADDRESS FIELD The address field indicates the starting address of a memory or register read or write sequence. Keep in mind that only odd starting addresses are allowed for the OTP ROM access. BYTES FIELD The bytes field indicates the number of data bytes to read or write, not including the CRC byte. Not all BYTES Field settings are supported. Only settings marked with an `X' are valid for a particular bus instruction, as indicated in Table 6. Attempting to read or write with an invalid BYTES setting may yield unpredictable results. Writing to OTP ROM can occur only two bytes at a time, but reading from OTP ROM can happen at 2, 4 or 16 bytes at a time. Writing to and reading from OTP ROM in any other byte denomination will yield unpredictable resuls and should therefore be strictly prohibited.
TABLE 6. DEFINITION OF THE BYTES FIELD BYTES FIELD 0 1 2 3 4 5-6 7 DATA BYTES TO FOLLOW 0 1 2 N/A 4 N/A 16 X X X Invalid selection. Causes a bus error. For reading from OTP ROM only (prior to lock-out). X X X X Invalid selection. Causes a bus error. OTP ROM WRITE OTP ROM READ REG READ OR WRITE CHLG CODE WRITE COMMENTS Invalid selection. Causes a bus error. Must use 1-Byte read for clearing of the STAT register.
12
FN6567.0 October 31, 2007
ISL6296A Bus Transaction Protocol
The XSD bus for the ISL6296A defines three types of bus transactions. Figure 11 shows the bus transaction protocol. The blue color represents the signal sent by the host and the green color stands for the signal sent by the device. Before the transaction starts, the host should make sure that the XSD device is not in the sleep mode. One method is to always send a `break' signal before starting the transaction, as shown in Figure 11. If the device is not in the sleep mode, the `break' signal is not mandatory. The `break' pulse width may appear to be wider than what the host sends out because of the reason explained in Figure 4. The symbols in Figure 11 are explained in Table 7.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL SYM DESCRIPTION MIN 0 BTH 1 BTD 1 BTH 1 BTD 800ms TYP MAX 800ms
Passive CRC Support
The CRC feature only supports the read transaction in the ISL6296A. When the OPCODE in the instruction is `10', an 8-bit CRC is automatically calculated for the data bytes being transferred out. The CRC result is then appended after the last data byte is read out. CRC is generated using the DOW CRC polynomial as follows:
POLYNOM = 1 + X + X + X
4 5 8
(EQ. 1)
IFGH Host inter-frame gap IFGD Device inter-frame gap TAH TAD Host turn-around time Device turn-around time
The CRC generation algorithm is logically illustrated in Figure 12. Prior to a new CRC calculation, the LFSR (linear feedback shift register) is initialized to zero. The read data to be transmitted out is concurrently shifted into the CRC calculator. After the actual data is transmitted out, the final content of the LFSR is the resulting CRC value. This value is transmitted out after the read data, with LSB being transmitted out first.
(A) Multi-Byte Write Instruction.
break TSD Write Instruction Frame IFGH Data Frame 1 IFGH Data Frame 2
(B) Multi-Byte Read Instruction.
break
TSD
Read Instruction Frame
TA D
Data Frame 1 (output from slave)
IFG D
Data Frame 2 (output from slave)
(C) Back-to-Back Transaction (Read Followed by Write). break TSD Read Instruction Frame
TA D
Data Frame (output from slave)
TA H
Next Instruction Frame
FIGURE 11. XSD BUS TRANSACTION PROTOCOL. THE `BREAK' SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
Serial Output
1st Stage LSB
2nd Stage
3rd Stage
4th Stage
5th Stage
6th Stage
7th Stage
8th Stage MSB
FIGURE 12. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
13
FN6567.0 October 31, 2007
ISL6296A
Analog Biasing Components and Clock Generation
The analog section in the ISL6296A mainly includes the Time Base Generator and the internal regulator for powering the circuits in the ISL6296A. TIME BASE GENERATOR A time base generator is included on-chip to provide timing reference for serial data encoding and decoding at the XSD bus interface. This eliminates the need for an external crystal. The time base oscillator is trimmed during manufacturing to a nominal frequency of 532.5kHz. It has a frequency tolerance better than 5% over operating supply voltage and temperature range. INTERNAL VOLTAGE REGULATOR The ISL6296A incorporates an internal voltage regulator that maintains a nominal operating voltage of 2.5V within the device. The regulator draws power directly from the VDD input. No external component is required to regulate circuit voltage. The regulator is shut off during Sleep mode. of the addressable registers are used nor implemented. Accessing an unimplemented register will result in the access instruction being ignored. A bus error indication may or may not be flagged. Bank 0 is dedicated for the OTP ROM. There are 16 memory locations implemented in the array. Writing to the OTP ROM has no immediate effect on the chip operation until a Power-on Reset occurred, or a soft reset is issued. Table 8 describes the OTP ROM memory assignment. The default factory setting for address [0:00] is given in Table 11. Bank 1 contains the Control and Status registers. Only 2 registers are implemented. Table 9 shows the register map of the Bank 1 registers. Detailed descriptions of register settings are given in Tables 14 and 15. Bank 2 contains the Authentication registers. Only 3 registers are implemented. These registers are used during the battery pack authentication process. Table 10 describes the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only, and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error.
Memory/Operational Register Description
The ISL6296A memory and register structure is organized into 4 banks of 256 addressable locations. However, not all
TABLE 8. OTP ROM MEMORY MAP (BANK 0) ADDRESS 0-00 0-01 0-02 0-03 0-04 0-05 0-06 0-07 0-08 0-09 0-0A 0-0B 0-0C 0-0D 0-0E 0-0F NAME DCFG DTRM SE1A SE1B SE1C SE1D SE2A SE2B SE2C SE2D SE3A SE3B SE3C SE3D INF1 INF2 DESCRIPTION Default Configuration Default Trimming Auth Secret #1A Auth Secret #1B Auth Secret #1C Auth Secret #1D Auth Secret #2A Auth Secret #2B Auth Secret #2C Auth Secret #2D Auth Secret #3A Auth Secret #3B Auth Secret #3C Auth Secret #3D General Purpose General Purpose BIT 7 BIT 6 BIT 5 BIT 4 BIT3 eINT BIT 2 ASLP TOSC[3:0] S1A[7:0] S1B[7:0] S1C[7:0] S1D[7:0] S2A[7:0] S2B[7:0] S2C[7:0] S2D[7:0] S3A[7:0] S3B[7:0] S3C[7:0] S3D[7:0] General purpose non-volatile memory for storage of model ID, date code, and other cell information BIT 1 BIT 0
DAB[1:0] HSF
SPD[1:0] TIBB[2:0]
SLO[1:0]
NOTE: Information stored in address 0-0E (INF1) and 0-0F (INF2) is for use by the host firmware only. Actual content depends on the host firmware customization preference.
14
FN6567.0 October 31, 2007
ISL6296A
TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1) ADDRESS 1-00 1-01 NAME MSCR STAT DESCRIPTION Master Control Device Status BIT 7 eEEW sEEW BIT 6 eINT sBER BIT 5 -sACC BIT 4 --BIT3 -DAB[1:0] BIT 2 -BIT 1 ASLP BIT 0 SRST
SLO[1:0]
TABLE 10. AUTHENTICATION REGISTERS (BANK 2) ADDRESS 2-00 2-01 2-05 NAME SESL CHLG AUTH DESCRIPTION Secrets Selection Challenge Code Register Authentication Code Register BIT 7 -BIT 6 -BIT 5 -BIT 4 -CHLG[31:0] AUTH[7:0] BIT3 BIT 2 BIT 1 BIT 0
CSL[1:0]
SSL[1:0]
TABLE 11. DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS BIT 7:6 NAME DAB[1:0] TYPE RW DEFAULT 00 DESCRIPTION Device Address Bit Setting: 00 : device responds only when CS field in instruction frame is'0' 01 : device responds to any CS field value in instruction frame 10 : device responds to any CS field value in instruction frame 11 : device responds only when CS field in instruction frame is `1' XSD Bus Speed Setting: Configures the bit rate of the XSD bus interface. 00 : 0.5x (2.89kbps) 01 : 1x (5.78kbps) 10 : 2x (11.56kbps) 11 : 4x (23.12kbps) Power-on default setting of eINT bit in the MSCR register. Power-on default setting of ASLP bit in the MSCR register. Secrets Lock-out Bits: Bit 1 : Read/Write lock-out bit for address locations 0-02 to 0-09 (Secret Set #1 and #2) Bit 0 : Read/Write lock-out bit for address locations 0-0A to 0-0D (Secret Set #3) NOTE: Once Bit 0 or Bit 1 is set, writing to the OTP ROM will permanently be disabled (after a reset cycle).
5:4
SPD[1:0]
RW
01
3 2 1:0
eINT ASLP SLO[1:0]
RW RW RW
1 1 00
TABLE 12. DEFAULT TRIMMING (DTRM) REGISTER SETTINGS BIT 7 6:4 3:0 NAME HSF TIBB[2:0] TOSC[3:0] TYPE R R R DEFAULT 0 --Unused Reference Current Trim Setting Oscillator Frequency Trim Setting DESCRIPTION
TABLE 13. LEGEND FOR THE TYPE COLUMN TYPE R W Read-only Write-only READ ACTION Data read Zeros read Data read Data read, then cleared Zeros read WRITE ACTION Data ignored Data written Data written Data ignored Data written, then cleard
ADDRESS 0-00: DEFAULT CONFIGURATION (DCFG) This address location stores the default configuration when the ISL6296A is manufactured. Table 11 describes each bit in detail. The legend for the TYPE column is given in Table 13. ADDRESS 0-01: DEFAULT TRIM SETTING (DTRM) This address location is writable only when the device is in test mode. During normal operation, any data written to it will be ignored. Table 12 describes the DTRM address in detail. ADDRESS 0-02/03/04/05: AUTHENTICATION SECRET SET #1 (SE1A/B/C/D) These address locations store the first set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[1] bit at OTP ROM location 0-00[1].
FN6567.0 October 31, 2007
RW Read/Write RC Clear after read WC Clear after write
<> Default setting loaded from designated OTP ROM bit locations W Writing disabled after lock-out
15
ISL6296A
ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET SET #2 (SE2A/B/C/D) These address locations store the second set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[1] bit at OTP ROM location 0-00[1]. ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET SET #3 (SE3A/B/C/D) These address locations store the optional third set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[0] bit at OTP ROM location 0-00[0]. Alternately, this memory space can be used to store additional cell information which can be accessed by the host. In this case, the SLO[0] bit should not be set.
TABLE 14. MASTER CONTROL REGISTER (MSCR) BIT 7 NAME eEEW TYPE R DEFAULT 0 <1/0> DESCRIPTION OTP ROM Write-in-Progress Interrupt Enable: When enabled, it allows the sEEW bit to flag an interrupt whenever the sEEW bit is set by its interrupt event. The eEEW bit is fixed at `1' when none of the OTP ROM lock-out bits are set. When any or both of the lock-out bits are set, the eEEW bit will become permanently `0' after a reset. Global Interrupt Enable: When enabled, it allows the sBER or sACC bit to flag an interrupt to the host whenever any of the respective interrupt events occurred. (Default setting loaded from OTP ROM location 0-00[3]) Unused. Auto Sleep Mode enable: When set, the ISL6296A will automatically enter Sleep mode after about 1s of XSD bus inactivity. When cleared, the device can only enter Sleep mode on Opcode command. (Default setting loaded from OTP ROM location 0-00[2]) Soft Reset: When a `1' is written and all registers are reset to their default states, all bus counters and timers are reset to their start-up conditions and device configuration information is reloaded from OTP ROM. After the reset sequence is complete, a `break' pulse is sent to the host. TABLE 15. DEVICE STATUS REGISTER (STAT) BIT 7 6 NAME sEEW sBER TYPE RC RC DEFAULT 0 0 DESCRIPTION OTP ROM Write-in-Progress Flag: This bit is set when attempt is made by the host to read from or write to the ISL6296A while the ROM is still processing the previous write instruction. XSD Bus Error Flag: This bit is set when one or more of the following occurrs at the bus interface: a) An invalid pulse width is received b) Bus activity is detected before the device completes its power-up sequence c) An invalid BYTES field in the instruction frame d) Improper authentication sequence is detected e) Reading secret information after the corresponding lock-out bits are set Register Access Error Flag: This bit is set whenever an instruction frame attempts to access a protected register as follows: a) Writing to OTP ROM after the ISL6296A has been locked out (any or both of the lock-out bits set) b) Accessing the ISL6296A is Test and Trim Registers when the device is not in test mode Unused Device Address Bit Setting: Loaded from OTP ROM location 0-00[7:6] during power-up. Secrets Lock-out Bits Setting: Loaded from OTP ROM location 0-00[1:0] during power-up.
6
eINT
RW
0 <1> 0 0 <1>
5:2 1
-ASLP
R RW
0
SRST
WC
0
5
sACC
RC
0
4 3:2 1:0
-DAB[1:0] SLO[1:0]
R R R
0 00 <00> 00 <00>
16
FN6567.0 October 31, 2007
ISL6296A
TABLE 16. SECRETS SELECTION REGISTER (SESL) BIT 7:4 3:2 NAME -CSL[1:0] TYPE R RW DEFAULT 0000 01 Unused Coefficient Definition Secret Selection: Selects the authentication secret code word stored in OTP ROM to be used as the coefficient definition code for the FlexiHash engine. 00: invalid selection 01: Authentication Secret Set #1 10: Authentication Secret Set #2 11: Authentication Secret Set #3 Seed Secret Selection: Selects the authentication secret code word stored in OTP ROM to be used as the secret seed for the FlexiHash engine. 00: invalid selection 01: Authentication Secret Set #1 10: Authentication Secret Set #2 11: Authentication Secret Set #3 DESCRIPTION
1:0
SSL[1:0]
RW
10
ADDRESS 0-0E/0F: GENERAL PURPOSE MEMORY (INF1/2) These address locations can be used to store information like model ID, date code, and other cell information, which can be read by the host. ADDRESS 1-00: MASTER CONTROL REGISTER (MSCR) The Master Control Register is defined in Table 14. The MSCR register can be both read or written by the host through the XSD bus. ADDRESS 1-01: DEVICE STATUS REGISTER (STAT) The STAT register is defined in Table 15. All status bits will be cleared upon a read to this register. The STAT is a readonly register. DDRESS 2-00: SECRETS SELECTION REGISTER (SESL) This register must be written to re-load the hash engine with secrets stored in OTP ROM prior to presenting a new challenge code word input. ADDRESS 2-01: CHALLENGE CODE INPUT REGISTER (CHLG) This register is used to input the 32-Bit challenge code generated by the host for device authentication. All four bytes of the challenge code should be written sequentially to this register, starting with the least-significant byte. After the fourth challenge byte is received, the authentication code generation process will start. This CHLG is a write-only register. ADDRESS 2-05: AUTHENTICATION CODE OUTPUT REGISTER (AUTH) This register is used to output the 8-Bit authentication code calculated from the 32-Bit challenge code. The register content may be read only once after each challenge code word is written to the device. Subsequent read to this register without a new challenge being input will result in an error condition.
Applications Information
XSD Bus Implementation
There are two ways to implement the XSD host in a microprocessor. One way is to use a spare UART (Universal Asynchronous Receiver/Transmitter). A GPIO (General Purpose Input/output) can be used if no UART is available for the XSD communication. Refer to Application Note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor.
Pull Up Resistor Selection
Since there is an internal pull-down current on the XSD pin, (as shown in Figure 8), it is important to choose a pull-up resistor value that is low enough so that the small amount of pull-down current through the resistor does not cause the bus voltage to droop below the VIH specification under any condition. 5k is a typical resistance used for pull-up.
Powered by XSD Bus
In applications where the device supply voltage is lower than 2.6V (such as an application powered by a single-cell NiMH battery), or a device that has no power source at all, the ISL6296A can be powered by the XSD bus. The application circuit is shown in Figure 2. The condition for the application circuit to function properly is that the bus pull-up voltage is 3.3V or 5V. The bus pull-up voltage will charge the capacitor C1 through an internal ESD diode, as shown in Figure 8. The ESD diode has 0.4V drop typically.
ESD Rating
The ISL6296A ESD specification is rated at 4kV of the human body model. When the ISL6296A is used in a handheld accessory, a higher ESD rating is typically required. External components are required to enhance the ESD performance.
Additional Application Information
See "Related Literature" on page 1 for additional application information.
17
FN6567.0 October 31, 2007
ISL6296A Small Outline Transistor Plastic Packages (SOT23-5)
D
P5.064
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.70 6 6 3 3 4 NOTES SYMBOL A MIN 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060 MAX 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.067
5 E 1 2 3
4 C L C L E1
A1 A2 b b1
e
C L 0.20 (0.008) M C L C
b
C
c c1 D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0374 Ref 0.0748 Ref 0.014 0.022 0.024 Ref. 0.010 Ref. 5 0.004 0.004 0o 0.010 8o
0.95 Ref 1.90 Ref 0.35 0.55 0.60 Ref. 0.25 Ref. 5 0.10 0.10 0o 0.25 8o
0.10 (0.004) C
L2 N R R1
5
WITH PLATING c
b b1 c1
NOTES:
Rev. 2 9/03
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C L1
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
18
FN6567.0 October 31, 2007
ISL6296A Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40
8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd
NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6567.0 October 31, 2007

▲Up To Search▲

Price & Availability of ISL6296ADRTZ-T

	To Download ISL6296ADRTZ-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .